This invention relates to testing of digital circuits. More particularly, it relates to a communications network comprising one of more nodes which incorporate boundary-scan logic for testing wherein the boundary-scan logic maybe exercised over the communications network.
Boundary-scan testing of integrated circuits is a well known technique for testing complicated digital circuits. ANSI/IEEE Standard 1149.1, IEEE Standard Test Access Port and Boundary-Scan Architecture has been developed to provide a commercial standard for boundary-scan testing and has been widely accepted by integrated circuit manufacturers
FIG. 1 shows conventional integrated circuit 10, which incorporates boundary scan logic for testing. Circuit 10 includes on-chip logic 20 to implement a predetermined function in a conventional manner. Logic 20 communicates with the external world through pins 22. To implement boundary-scan testing a test data register 30 of cells 32 is also included on integrated circuit 10. Cells 32 are connected between logic 20 and pins 22 and are also connected to form a serial shift register.
Integrated circuit 10 also includes a Test Access Port TAP comprising pins 40, 42, 44, 46 and 48 for, respectively, connection of a test data input signal TDI, a test clock TCK, a test mode select signal TMS, a test data output signal TDO, and an optional reset signal TRST. Signals TCK and TMS are connected through pins 42 and 44 to a TAP controller 34 together with, if provided, reset signal TRST through pin 48. Data TDI is connected through pin 40 to test data register 30 and to instruction register 36. Output data is connected to pin 46 through control 38 from either array 30 or instruction register 36 to provide signal TDO.
FIG. 2 shows a more detailed block diagram of the boundary-scan logic of FIG. 1. TAP controller 34 is a state machine which generates clocks and controls to control the operation of the boundary-scan test logic in response to control signals TMS which are clocked by clock TCK. Controller 34 maybe reset by signal TRST; though in the preferred embodiments discussed herein TRST is not used. In response to controller 34 data TDI is shifted into either test data registers 30 or instruction register 36. As data is shifted into registers 30 and 36 previous data is shifted out through circuit 38 to provide, under control of controller 34 output signal TDO.
Under control of instruction register 36 data in test data register 30 can be applied to the inputs of logic 20, or output pins of pins 22, or the state of pins 22 maybe loaded into corresponding cells 32 of register 30. After the test data is applied and the results capture the results are shifted out of register 30, as new test data is shifted in, and returned for analysis.
Those skilled in the art will be aware that boundary-scan logic, as defined in Standard 1149.1 includes numerous other features which have not been described, and which are not considered necessary for an understanding of the subject invention.
While boundary-scan testing, as described above, has gained wide acceptance its use heretofore has been largely limited to physically compact systems where parallel signal interconnection is provided through motherboards or backplanes or similar techniques, where the addition of four or five extra wires for control of the boundary-scan logic is not of major consequence. Boundary-scan logic has been of less advantage in more physically distributed systems comprising one or more control nodes interconnected by a communications network. In such systems a major design criteria is to reduce the number of signal lines or channels necessary for the distribution of signals among the various nodes. In many such systems serial communications is used for this purpose.
Thus, it is an object of the subject invention to provide a system for control of boundary-scan test logic in a communications network comprising a plurality of control nodes.